1. Field of the Invention
The invention relates generally to complementary metal oxide semiconductor (CMOS) structures, and methods for fabricating CMOS structures. More particularly, the invention relates to CMOS structures with enhanced performance, and methods for fabricating those CMOS structures.
2. Description of the Related Art
In addition to stand alone transistors (i.e., including field effect transistors (FETs), as well as bipolar transistors), resistors, diodes and capacitors, semiconductor structures also often include CMOS structures. A CMOS structure includes a complementary doped pair of field effect transistor devices including a pFET device and an nFET device. CMOS structures and CMOS devices are desirable within the semiconductor fabrication art insofar as semiconductor circuit configurations that are based upon CMOS structures and CMOS devices provide for reduced power consumption in comparison with alternative semiconductor circuit configurations that are not based upon CMOS structures and CMOS devices.
In addition, CMOS structures and CMOS devices have been successfully scaled in dimension for several decades to provide for continued enhancements in semiconductor circuit performance and semiconductor circuit functionality.
While CMOS structures and CMOS devices are quite common in the semiconductor fabrication art, similarly with other semiconductor structures and semiconductor devices they are not entirely without limitations.
In that regard, as CMOS structure and CMOS device dimensions continue in a scaled decrease, lithographic limitations for uniformly fabricating individual pFET and nFET components (i.e., such as but not limited to gates) with desirable resolution and dimensional control within a particular CMOS structure becomes increasingly more challenging.